Floating Point FPGA: Architecture and Modelling

Abstract—This paper presents an architecture for a reconfigurable device which is specifically optimised for floating point applications. Fine-grained units are used for implementing control logic and bit-oriented operations, while parameterised and reconfigurable word-based coarse-grained units incorporating word-oriented lookup tables and floating point operations are used to implement datapaths. In order to facilitate comparison with existing FPGA devices, the virtual embedded block (VEB) scheme is proposed to model embedded blocks using existing FPGA tools. This methodology involves adopting existing FPGA resources to model the size, position and delay of the embedded elements. The standard design flow offered by FPGA and CAD vendors is then applied and static timing analysis can be used to estimate the performance of the FPGA with the embedded blocks. On selected floating point benchmark circuits, our results indicate that the proposed architecture can achieve 4 times improvement in speed and 25 times reduction in area compared with a traditional FPGA device.